It's the logic that generates the other synchonized signals that really defines the delays you're seeing.ġ. The module you've produced could be digested to a simple clocked always block with one line each in the "if( reset )" and "else if( tx_clk )" branches, actually increasing readability and understanding.
Concatenation is also a very useful item for both the rhs and lhs of the equation. I wouldn't use a separate always block and I'd use a conditional operator (a<=b?c:d ) for load vs shift. If the external trigger could occur immediately after a frame is completed (or sooner?!) additional logic would be used to guarantee proper handling of the synchronized control. I suspect that your tx_clk strobe is registered again to add another 20ns rather than using a combinatorial value (wire) from your registered external signals and their delayed version.Ī question for you to help consider the functionality of your code: what happens between frames? Do you expect to be sitting in the idle state? Do you expect to be actively shifting an empty shift register (all zeros)?Īs a seasoned FPGA guy, I'd design the shift register without states with a load that occurs on the external trigger and shift for the rest of the time. This could be reduced by sampling the trigger on the 50 MHz falling edge and using this synchronized value on the rising edge reducing the additional synchonization delay to 10-20ns.
To properly synchronize an external trigger or slow clock to the 50MHz domain would typically take 20-40ns: one clock edge to sample the external signal, the next clock edge to use the single sampled value across all dependent registers. It must be the generation of the tx_clk strobe where most of the delay is felt. Since your description suggests both tx_clk and frame_end are synchronized to the 50MHz and tx_clk occurs 1 out of every 10 clocks, a delay in frame_end would cause a 200ns additional output delay. The clk edge produces a txout when txclk is active while in the idle state. To see where all the delays are, you'd have to show how the tx_clk strobe and frame_end are generated since the shifter you describe has no more delays beyond what those signals cause. Is tx_clk a 5 MHz strobe (1 high in 10 periods) in the 50MHz time domain? If not, some assumptions here are invalid. What can be done in order to minimize the delay? I can see delay of ~ 80 nsec, between the external clock and the output data. I have designed this register and synchonized the 5 MHz external trigger (pseudo clock txclk) to the 50 MHz clock. The output serial data should be synchronized to the external clock (5 MHz). The external trigger and the board clock ( 50 MHz ) are not synchonized. My board clock is 50 MHz and I also have an external trigger ( ~ 5 MHz, pseudo clock). Would like to design a parallel in serial out shift register.
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